The present invention relates generally to the field of integrated circuit manufacturing and more particularly to testing an integrated circuits, module substrates, system boards, and attached cables.
Due to the small geometries at the chip controlled collapse chip connection (C4) level it is very difficult to be able to launch a high quality signal at the top of a substrate at the chip interface in order to analyze the signal path from the chip, interface, through the substrate and on to a motherboard and other components such as cables and cards that may be in that path.
A common way to test the quality of a high signal is to evaluate it in a fully functional system using integrated circuits that designed to capture the data being transferred between driver and receiver. While this method is effective in determining if the systemfunctions correctly it is limited since the transmitted signal cannot be significantly changed and the received waveform cannot be analyzed in detail. The embodiment herein does not require a functional system nor does it require an integrated circuit to be present. This allows signal integrity measurements of selected paths on a system before it becomes fully functional without the presents of an integrated circuit.
The traditional testing method without an integrated circuit present is to use pico-probes to inject a signals at the top surface of the substrate. This method is limited by the fact that the dimension of the C4 pad and the spacing between the C4 pads is small while the size of the pico-probe is large with respect to these pads. This limits the number of probes that can be connected to the top surface of a substrate disrupt the quality of the signal being injected since the probe itself creates a discontinuity in the impedance of system. The gross mismatch in pad to probe geometries also limit the selection of signal that can be simultaneously contacted which limits the scope of what is possible to analyze. Another approach would be to re-design the substrate (chip carrier or module) to spread out the C4 pads to make them more accessible. However, this may significantly alter the integrity of the substrate and the internal wiring to an extent where it does not truly represent the impedance network that will be seen by the actual product leading to false assumptions about the integrity of the signal path.
Hence, there exists a need to improve the testing of signal integrity of wiring in a substrate.